Complementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET) has provided significant improvement in the speed performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges are faced when CMOS devices are scaled into the sub-100 nm regime. An attractive approach for additional improvement of CMOS transistor performance exploits strain-induced band-structure modification and mobility enhancement to increase the transistor drive current. Enhanced electron and hole mobility in silicon (Si) under biaxial tensile strain can be achieved. Enhanced electron and hole mobilities improve the drive currents of N-channel and P-channel MOSFETs, respectively.
Various designs of strained silicon layers for transistor fabrication utilize thick buffer layers or complex multi-layer structures on bulk silicon substrates. As shown in FIG. 1A, a device 10 utilizing conventional strained Si substrate technology employs a thick silicon-germanium (SiGe) graded buffer layer 12 with thickness in the order of micrometers formed on a Si substrate 14. Such a thick graded buffer layer 12 requires an extended length of time, i.e., of several tens of minutes to several hours, to grow and is an expensive process. A relaxed SiGe layer 16 is then deposited overlies the graded buffer layer 12. The relaxed SiGe layer 16 has a larger natural lattice constant than that of silicon. As a result, a thin layer 18 of silicon that is epitaxially grown on the relaxed SiGe layer 16 will be under biaxial tensile strain. This is shown in FIG. 1B. Transistors fabricated on this strained silicon layer 18 will have enhanced electrical performance. However, such a substrate might not be easily or economically introduced into a conventional CMOS process. The integration of strained layers into a conventional CMOS process introduce significant difficulties. This is because conventional CMOS process utilize high processing temperatures, especially during the formation of isolation structures.
Isolation structures such as shallow trench isolation (STI), local oxide of silicon (LOCOS), and their variants are in widespread use on bulk substrates today. High temperatures favor the relaxation of strained layers and the formation of dislocations. The dislocation density in strained layers has been observed to increase with prolonged annealing at high temperatures. Since starting substrates with strained layers are subjected to the high thermal budget of the isolation formation process, the integration of strained layers on bulk substrates is very challenging. In U.S. Pat. No. 6,429,061, the strained silicon layer is grown selectively after isolation structures are formed to avoid the high temperatures of the isolation formation process. In spite of this, U.S. Pat. No. 6,429,061 employs an expensive thick SiGe buffer layer and a selective strained silicon epitaxial process.
Another type of substrate, silicon-on-insulator (SOI) substrates, though offer several advantages over bulk substrates, are not as widely used as bulk substrates. In SOI technology, MOSFETs are formed on a thin layer of silicon overlying a layer of insulating material such as silicon oxide. Devices formed on SOI substrates offer many advantages over their bulk counterparts, including reduced junction capacitance, absence of reverse body effect, soft-error immunity, full dielectric isolation, and absence of latch-up. SOI technology therefore enables higher speed performance, higher packaging density, and reduced power consumption. Since it is not straightforward to incorporate a strained silicon layer on a SOI substrate, strained silicon-on-insulator (SSOI) substrates are in an initial stage of research.
Others have attempted to fabricate transistors on a strained silicon layer overlying two SiGe layers with different Ge contents which is provided on an insulator layer. In U.S. Pat. No. 6,410,371, a method of forming a semiconductor-on-insulator (SOI) wafer with a Si/SiGe/Si heterostructure is disclosed, where the topmost silicon layer is strained. These works teach the formation of SOI substrates comprising of Si and SiGe layers where the Si layer is strained. The presence of SiGe in the semiconductor layer introduces problems in the formation of liner oxide in the STI process. STI process also potentially relaxes the strained silicon layer.
MOSFETs with strained silicon channels have enhanced carrier mobilities. Most of the research work on strained silicon transistors employed bulk substrates, where a pseudomorphic strained silicon layer is epitaxially grown on a relaxed silicon-germanium (Si—Ge) layer. The relaxed SiGe layer overlies a thick SiGe graded buffer layer on a silicon substrate (as shown in FIGS. 1A and 1B). Such bulk substrates employ isolation structures such as shallow trench isolation (STI) to isolate devices from one another. The STI formation process typically comprises of a trench formation step, a liner oxide formation step, a trench filling step, and an annealing step. The liner oxide formation step, in the case of the strained silicon substrate, involves the oxidation of SiGe. This results in a liner oxide of poor quality and leads to leakage problems and poor device isolation.
Research work on a SiGe-free SOI substrate where strained silicon is incorporated has also been reported. The elimination of SiGe in the semiconductor layer of the SOI substrate alleviates problems with liner oxide formation in the STI process. However, the STI process still involves high temperatures that might relax the strained silicon layer.
It is therefore an object of the present invention to provide a silicon-on-insulator semiconductor device utilizing strained silicon technology.
It is another object of the present invention to provide a silicon-on-insulator semiconductor device that can be fabricated without the drawbacks or shortcomings of the conventional manufacturing methods.
It is a further object of the present invention to provide a highly manufacturable strained silicon-on-insulator transistor with mesa isolation.
It is another further object of the present invention to provide a fabrication process for strained silicon-on-insulator technology with reduced thermal budget.